SAR-ADCs are a specific type of ADC which typically use a capacitive array which stores a sample of an analog input voltage. One side of the capacitors in the capacitive array is coupled to an input voltage and the other to a reference voltage. This reference voltage is typically somewhere between two other reference voltages. This voltage is referred to as a mid-voltage although it is not necessarily in the exact middle of the supply voltage range or in the exact middle between the two other reference voltages, the supply voltage VDD and ground. After sampling the input voltage, switches open to store a charge on capacitors of the capacitive array. All capacitors of the array are coupled with one side to a common node, which is coupled to one input of a comparator. The other input of the comparator receives a comparator reference voltage. After initial sampling, the mid-voltage is also removed from the common input node. During conversion, the other side of each capacitor of the capacitive array is switched between two voltages. These two voltages are typically two reference voltages with the first reference voltage being ground and the second voltage being a specific voltage that allows the value of the input voltage to be determined step by step. In each step, a single capacitor of the array is switched from one reference voltage to another to redistribute the charge on the capacitors through the common node. The voltage on the common node changes accordingly and the comparator detects whether it is greater or smaller than the reference voltage. Thus the digital value representing the analog input voltage is determined step-by-step.
While the input nodes are connected to the mid-voltage during the sampling phase, the comparator undergoes autozeroing. Any offset introduced by the comparator is determined during this autozeroing and the AD-conversion phase uses a compensated comparator.
During the sampling steps when the mid-voltage is no longer applied and switches are open, additional undesired charge is injected from the switches into the input nodes of the comparator. To avoid this effect the input nodes, the switches and the capacitances are made strictly symmetric. This symmetric design insures charges caused by switching will only cause a common mode voltage. This voltage is suppressed by the common mode rejection ratio (CMRR) of the comparator. However, the CMRR is limited. Any unbalance between the input nodes, the capacitive loads or the switches may result in a differential voltage input voltage to the comparator. This can severely degrade the conversion results. SUMMARY OF THE INVENTION
An object of the present invention is a method and a device to reduce effects due to charge injection during the adjusting step of a comparator in an SAR-ADC.
Accordingly the present invention is a method for controlling a successive approximation register analog to digital converter. In a sampling phase, a first switch connects one side of a capacitor with an input voltage. A second switch connects the other side of the capacitor to a mid-voltage. This second side of the capacitor is coupled to a first comparator input. The first switch and the second switch then open and the comparator performs autozeroing.
The first switch connects one side of a capacitor not connected to the comparator input or to the mid-voltage to an input voltage. The capacitor may be a capacitive array. The capacitor is connected to one input of a comparator such as the positive input. A second switch additionally connects the side of the capacitor that is connected to the comparator input to a mid-voltage. This mid-voltage may equal half the positive supply voltage (VDD/2). During the sampling phase, the first and second switches are closed connecting the capacitor to both the input voltage and the mid-voltage. After sampling the input voltage, the first and second switches open disconnecting the input voltage and the mid-voltage from the capacitive array. The comparator performs autozeroing while the comparator's input nodes are decoupled from the mid-voltage. Consequently, the autozeroing considers the error charge injected into the capacitive array by the first and second switches and completely cancels the effect of this parasitic charge injection. This produces an offset-free transfer function in the analog to digital converter.
Preferably, the autozeroing samples an offset voltage at the first comparator input including the error charge injected into the capacitive array due to opening the first and second switches. This cancels the offset voltage at the first comparator input. Opening the first and second switches causes a charge injection offset voltage at the input of the comparator. This offset voltage is sampled using sampling circuitry inside the comparator, which can be a capacitor. In addition standard autozeroing circuitry can be used.
A third switch can be provided which is closed during the sampling phase. This third switch connects the second comparator input (for example the negative input) to the mid-voltage. Connecting both input nodes to the mid-voltage permits the offset of the comparator to be determined. If the charges injected by the second and third switches were equal, only common mode voltage would appear at the comparator's input nodes. However, any imbalance of the input nodes and the capacitances of the input nodes leads to differential voltages and therefore to incomplete offset cancellation. The present invention provides that the autozeroing includes the effects induced by opening the second and the third switches. Accordingly, the autozeroing is only carried out or continued until the first, second and third switch are all opened.
Ideally the method continues the autozeroing for a predetermined time after opening the first, second and third switches. The comparator and the autozeroing circuitry inside the comparator take some time to settle after the switches open. In other words, it takes some time for the autozeroing to cancel the effect of the parasitic charge injected when the switches open. The autozeroing should continue for the time it takes the comparator to settle. In this way, the comparator has time to fully cancel the effect of the parasitic charge injection and associated offset voltage. This can be implemented, for example, by changing the sequence clocking in the SAR state machine.
The present invention also provides an electronic device including a control circuit controlling a successive approximation register analog to digital converter. The control circuit comprises a comparator, a capacitive array having a capacitor with one side configured to be coupled to a first input of the comparator and switches. The control circuit closes a first switch connecting one side of the capacitor of the capacitive array to an input voltage, closes a second switch connecting the other side of the capacitor to a mid-voltage. The second input of the comparator can be switched to a mid-voltage by a third switch. The control circuit then performs autozeroing of the comparator only when the first and second switches open and, if there is a third switch, when the third switch opens. During the sampling phase of the input voltage onto the capacitive array, the inputs of the comparator are switched to the mid-voltage by closing the second and third switches. The comparator may already be set in an autozero mode. However, the comparator stays in autozeroing mode after the mid-voltage is disconnected from the capacitive array by opening the second switch. Any induced error charge will then be considered when autozeroing the comparator and will not interfere with the analog to digital conversion. The comparator in its autozero mode should have enough time to settle after the charge injections into the capacitive array due to opening of the first, second and third switches.
The present invention provides a SAR state machine, which performs a sequence of clocking an SAR capacitive digital to analog converter (CDAC, i.e. the capacitive array coupled to the input of the comparator) to provide sufficient delay between opening the switches coupling the inputs of a comparator to a mid-voltage and autozeroing of the comparator.
The electronic device comprises an autozeroing circuit configured to sample an offset voltage at an input of the comparator. The present invention aims to remove any offset voltage due to opening the switches, but the offset cancellation will include also the internal offset of the comparator. The effect of the offset voltage, caused by the parasitic charge injection upon opening of the switches, is then cancelled at the input of the comparator by the autozeroing circuit and does not affect the analog to digital conversion. The autozeroing circuit may include a chain of comparator stages. Each of the stages comprising a comparator having an input for receiving the offset voltage and an output connected to a sampling capacitor for sampling the offset voltage.
Advantageously, the device may further comprise a delay circuit to prolong the autozeroing for a predetermined time after the control circuitry has opened the first, second and/or third switches. After the switches open and inject a parasitic charge into the capacitive array, the comparator takes some time to settle during the autozeroing before it can fully cancel the effects of the error charge and associated offset voltage. Continuing the autozeroing for a time equal to the settling time of the comparator means that the comparator has enough time to settle and that the error charge will be fully offset. The delay circuit can be implemented in the sequence clocking in the SAR machine, which can be configured to prolong the autozeroing to be equal to the settling time of the comparator.